The invention relates to the transmission of digital data and more specifically to a device for synchronizing digital data transmitted in the form of packets.
In order to prevent the interception of data by a third party for whom they are not intended, instead of using a given carrier frequency throughout the transmission time, certain digital data transmission systems, after compression, group the data into packets; the latter are separated by given time intervals and each packet is transmitted by modulating a given carrier frequency. Thus, there is a frequency jump between two successive packets. The time separating the packets is that necessary for ensuring that the transmitter and receiver (filters, synthesizers, etc.) are tuned to the frequency corresponding to the next packet. This type of transmission is called frequency evasion transmission.
During the reception of messages it is necessary to synchronize the receiver on the basis of the data received. Thus, the rhythm of the bits forming the message is known by the receiver, but the phase thereof is not known and on the basis of the data received it is necessary to reconstitute a clock in phase with the data bits.
This synchronization is carried out in conventional devices either only at the start of the message (and is possibly repeated during transmission) or permanently, a clock at the frequency of the bits being controlled by the data received by appropriate means making it possible to become independent of the noise affecting the received bits.
In frequency evasion transmission systems where the data are transmitted in packets on carriers at different frequencies as indicated hereinbefore, the problem of synchronization is complicated by the fact that the phase swings on the received data can vary as a function of the carrier frequency used for the transmission, even if the propagation conditions are otherwise unchanged and if the transmission and reception stations are fixed. The phase swings vary, affortiori, if the propagation conditions vary or if at least one of the stations, i.e. transmitter or receiver is movable.
Consequently in such systems it is necessary to synchronize a receiver clock with the data received, said clock being readjusted for each packet of bits received, the phase swing being almost constant throughout the transmission time of a single packet.
In order to bring about the synchronization of the receiver clock with the bits received, the latter forming all the bits constituting the transmitted message, a synchronization device is known which essentially comprises a delay line and a synchronization circuit in parallel, both of which receive the bits after demodulation of the carrier. The time lag introduced by the delay line is such that the receiver clock is adjusted in phase with the bits when the latter pass out of the line. Thus, the synchronization circuit uses the received bits for carrying out the synchronization and for determining the phase swing takes account of a certain number of successive bits. This smoothing introduced by the synchronization circuit makes it possible to obviate the necessity of fixing the phase swing at a value which would take account of the noise affecting the bits received.
Such a device is not adapted to the synchronization of binary messages transmitted in packets, each packet having a phase swing differing from that affecting the previous packet due to the carrier frequency jump, because the bits at the end of a packet would be sampled by a clock signal adjusted in phase by a circuit taking account of the bits of the following packet, whose phase swings are different.